1. Field of the Invention
The present invention relates to a method of forming a plug, relates more particularly to a method of forming a plug embedded in a via-hole of a semiconductor device having multilayer wirings.
2. Description of the Related Art
A semiconductor device with highly integrated semiconductor elements is provided with wirings multilayered in the device concerned. The wirings are configured to reduce wiring widths and wiring gaps in order to integrate highly the semiconductor elements. Since delay of a signal is enlarged due to an increase in capacitance between wirings resulting from the reduction in the wiring widths and wiring gaps, a material with low dielectric constant has been used as an interlayer insulating film between the wirings for reducing the delay.
As a low dielectric constant material, for example, counted is silicon oxide with dielectric constant of around 2.5 comprising Silsesquioxane (Si2O3) as the main raw material or Silsesquioxane with Si—H radical or Si—CH3 radical as the main raw material. However, a typical low dielectric constant material comprising Silsesquioxane except oxide with fluorine addition as the main raw material is liable to be eroded by a WF6 gas. Further, it is also known that the low dielectric constant material is generally weak in heat treatment in oxygen and in oxygen plasma, and is liable to be oxidized by active oxygen generated in oxygen plasma through an ashing process with oxygen plasma called as “ashing”.
Now, a conventional method of producing such kind of semiconductor device 100 will be described referring to FIG. 10 and FIG. 11.
FIG. 10 shows a conventional semiconductor device 100 on the way to production.
In FIG. 10, afterforming a lower layer wiring 12 at a predetermined location using a predetermined pattern on a semiconductor substrate 11 with semiconductor elements not shown in the figure, an interlayer insulation film 13 is formed using a low dielectric constant material represented by Silsesquioxane covering the lower layer wiring 12 and the semiconductor substrate 11. Then, forming an oxide film 14 over the interlayer insulation film 13, a via-hole 16 is formed using a resist film for selectively etching the oxide film 14 and the interlayer insulation film 13. Next, while removing the resist film having been used for forming the via-hole by an ashing process called “ashing”, a silicon dioxide film is formed as a guard film 18 on the inner wall of the via-hole 16. Then, after forming a barrier metal film 22 over the oxide film 14 by sputtering, a plug is formed in the via-hole 16.
Adding to the conventional semiconductor device above, there are a conventional semiconductor device having a protective film and a barrier metal film for preventing erosion against an interlayer insulation film and a conventional semiconductor device having an organic SOG (Spin-On-Glass) protective layer and a barrier film (refer to FIG. 1 and FIG. 4 in JP, 11-297829, A).
The protective film and the organic SOG protective layer are formed for preventing erosion against the interlayer insulation film by a stripping solution during removing the resist film having been used out for forming the via-hole by the wet stripping solution concerned.
Further, with regard to a semiconductor device formed using an interlayer insulation film, which is selectively etched, there are a conventional semiconductor device having an adhesive layer and a conventional semiconductor device having a barrier layer in place of the adhesive layer concerned (refer to FIG. 1 and FIG. 2 in JP, 2001-118925, A).
The adhesive layer is formed between a plug formed in a via-hole and an interlayer insulation film in order to make the plug adhere to the interlayer insulation film, and the barrier layer is formed for preventing diffusion of a copper wiring and a copper plug from the via-hole to the interlayer insulation film.
Besides, in a conventional semiconductor device 100, as shown in FIG. 11, although an inner wall of a via-hole is protected with a guard film 18 and a barrier metal film 22, the inner wall of the via-hole has been eroded by the WF6 gas used for forming a plug.
Here, the present inventor found out that the cause of erosion of the via-hole's inner wall was due to etching of a lower layer wiring 12 by sputtering during a formation process of the via-hole 16. That is to say, it was found that when the lower layer wiring 12 was exposed as the etching process proceeded, the top portion of the lower layer wiring 12 concerned was sputtered, and the surface of the lower layer wiring 12 was shaved off, and the dust as a residue 17 (refer to FIG. 11) stuck to the inner wall of the via-hole. It was also proved that a residue 17 was significantly generated when a borderless via-hole is formed at the unmatched location above the lower layer wiring 12. The reason is considered because an edge portion of the lower layer wiring 12 is liable to be shaved off, as the strength of the edge portion of the lower layer wiring 12 concerned is weak.
On the other hand, when a resist film having used for forming the via-hole is removed, an ashing process using oxygen plasma, so-called ashing, is performed as mentioned above. However, it was also found in the ashing process that since the oxygen plasma is accelerated to radiate in the direction from the top toward the bottom of the interlayer insulation film 13 through which the via-hole 16 is formed, the oxygen plasma is shielded by the residue 17 and consequently a guard film is not formed on the inner wall below the residue sticking to the via-hole 16.
Further, it was also found that the guard film 18 was not formed only on the inner wall below the residue 17 but also on the periphery, to which the residue is sticking, of the inner wall of the via-hole 16.
Further, although a barrier metal film 22 is formed by depositing titanium nitride (TiN) by sputtering where metal is physically deposited, it was also found out that the barrier metal film was not formed on the inner wall of the via-hole shielded by the residue 17, so that the guard film was not formed on the lower portion of the inner wall of the via-hole.
In the case where the guard film 18 and the barrier metal film 22 is not formed on the lower portion of the inner wall of the via-hole 16, as shown in FIG. 11, once a CVD (Chemical Vapor Deposition) process using the WF6 gas for forming a plug is performed, the interlayer insulation film 13 is eroded at the lower portion of the inner wall of the via-hole or the inner wall around the residue 17 which is not covered by the guard film 18 and the barrier metal film 22. That is to say, erosion occurs due to direct contact of the interlayer insulation film 13 with the WF6 gas.